1. Field of the Invention
This disclosure relates to nonvolatile memory devices and methods of fabricating the same and, more particularly, to floating trap type nonvolatile memory devices and methods of fabricating the same.
2. Description of the Related Art
The importance of nonvolatile semiconductor memories has been emphasized together with dynamic random access memories (DRAMs) and static random access memories (SRAMs). Unlike volatile random access memories (RAMs) that temporarily store used data, nonvolatile memory devices can maintain stored data even if power is cut off. In particular, electrically erasable and programmable read only memories (EEPROMs) are considered as preferable among the nonvolatile memories, because EEPROMs are capable of programming and erasing data, and readily rewriting data.
EEPROMs can be typically categorized as either bit erase memories capable of erasing and reading data in bits, or flash memories capable of erasing data in blocks of several tens to several hundreds bytes or more and writing in bits. Because the bit erase memory may selectively erase and program data in bits, the bit erase memory is easily used and applied. However, the bit erase memory needs two transistors, i.e., a memory transistor and a selection transistor, therefore, a chip size is large and the corresponding price is high. On the other hand, the flash memory is capable of programming data in bits, and erasing in all bits or in blocks. Since a memory cell of the flash memory includes one transistor, the area of the cell is relatively small.
The flash memories can be typically divided into NOR-type structures and NAND-type structures. In the NOR-type structure, cells are disposed in parallel between a bit line and a ground. In the NAND-type structure, cells are disposed in series between a bit line and a ground. 
FIG. 1A is a top plan view illustrating a NAND-type structural cell according to a conventional method, and FIG. 1B is an equivalent circuit diagram illustrating the NAND-type structural cell of FIG. 1A.
Referring to FIG. 1A, a field region defines an active region 2. A word line 4 is disposed to cross the active region 2 and the field region. An area where the word line 4 crosses the active region 2 corresponds to a gate electrode 6 of a transistor. A bit line 8 is disposed at right angles to the word line 4. Reference numeral A represents a cell that is a memory data unit.
FIG. 2A is a top plan view illustrating a NOR-type structural cell according to a conventional method, and FIG. 2B is an equivalent circuit diagram illustrating the NOR-type structural cell of FIG. 2A.
Referring to FIG. 2A, a field region 12 defines an active region. A word line 14 is disposed to cross the active region and the field region 12. An area where the word line 14 crosses the active region corresponds to a gate electrode 16 of a transistor. Impurity ions are implanted into the active region of both sides of the gate electrode 16, thereby forming a source region 18 and a drain region 20. A contact 24 is formed in the drain region 20 to be connected to the bit line 22 formed at right angles to the word line 14. Reference numeral B represents a cell that is a memory data unit.
Functionally, the NAND-type flash memory has slower reading speed than the NOR-type flash memory, and has a restriction of reading and writing data by taking a number of cells connected in series to the NAND-type cell array as one block. However, as the NAND-type flash memory has a smaller cell area, fabrication costs per bit can be reduced.
The flash memory devices are either floating gate type or floating trap type. SONOS (polysilicon-oxide-nitride-oxide-silicon) structural devices are well known as a floating trap type.
While the floating gate device injects electric charges into a floating gate, the SONOS device injects electric charges into a trap disposed in a silicon nitride layer. The floating gate device has the limit of decreasing a cell size, and is subjected to high voltages for program and erase operations. On the other hand, the SONOS device meets the needs of low power and low voltage, and enables high integration.
FIGS. 3A and 3B are cross-sectional views illustrating a SONOS device according to a conventional method.
Referring to FIG. 3A, a gate insulation layer 47, which includes a lower insulation layer 42, a charge storing layer 44, and an upper insulation layer 46, is formed on a substrate 40. A gate conductive layer 48 and a silicide layer 50 are formed on the gate insulation layer 47. The gate conductive layer 48 and the silicide layer 50 are selectively etched using a hard mask pattern 52 formed by a photolithographic process. As a result, a gate stack is formed to expose a surface of the substrate 40. During the etch process, surfaces of the gate electrode 48 and the substrate 40 are damaged. Oxidization should be performed to remove the etching damages. Thus, thermal oxide layers 54a and 54b are formed on sidewalls of the gate electrode 48 and on the silicon substrate 40. At this time, a lateral diffusion of oxygen occurs at boundaries between the semiconductor substrate 40 and an edge of the lower insulation layer 42 of the gate insulation layer 47. This results in a gate bird's beak 56 that causes a thickness of the edge of the lower insulation layer 42 to be increased. Due to the gate bird's beak 56, while a dispersion of a threshold voltage Vth of the cell increases, write/erase speed is lowered. Continuously, impurity ions are implanted into the active region by using the gate stack as an ion implantation mask, to form an impurity region 58 that corresponds to a source/drain region.
Referring to FIG. 3B, in order to prevent the foregoing gate bird's beak 56, a method of patterning the gate electrode 48 without etching the gate insulation layer 47 is proposed. In this case, a nitride layer is used as the charge storing layer 44 that serves as a barrier to oxygen diffusion during the oxidization process for removing the etching damages of the patterned gate electrode 48. In other words, because the oxygen is cut off by the charge storing layer 44, the bird's beak is not generated in the lower insulation layer 42 that is an oxide layer. Nevertheless, in the subsequent ion implantation process for forming the source/drain region, the exposed upper insulation layer 46 is attacked due to the ion implantation. As a result, the nonvolatile memory device does not normally program and erase data. In addition, an adhesion between the upper insulation layer and an interlayer dielectric layer (ILD), which will be formed in a subsequent process, is weakened by defects due to the ion implantation process.
Embodiments of the invention address these and other limitations of the prior art.